1. Field of the Invention
The present invention relates to circuit design and, more particularly, to techniques for performing timing estimation in circuits specified using hardware description languages.
2. Related Art
Integrated circuits (ICs) are becoming increasingly large and complex, typically including millions of individual circuit elements, such as various kinds of passive elements and logic gates. Very Large Scale Integrated (VLSI) Circuits are too large and complex for a circuit designer, or even a large team of circuit designers, to manage effectively on an element-by-element basis. As a result of this increased size and complexity, IC designers are increasingly using electronic design automation (EDA) software tools to assist with IC design. Such tools help to manage the complexity of the design task in a variety of ways, such as by allowing ICs to be designed hierarchically, thereby enabling the design to be divided into modules and enabling the design task to be divided among multiple designers in a manner that limits the complexity faced by any one designer.
Various hardware description languages (HDLs) have been developed which allow circuit designs to be described at various levels of abstraction. A description of a circuit according to an HDL (referred to herein as a “model” or “specification” of the circuit) may, for example, describe a particular circuit design in terms of the logic gates in a digital system. Descriptions of a circuit at different levels of abstraction may be used for different purposes at various stages in the design process.
For example, one of the first steps in designing a modern microprocessor is to describe the functions performed by the processor using statements written in a Register Transfer Language (RTL), which is an example of an HDL. In general, an RTL is a language for describing the behavior of computers in terms of step-wise register contents. RTL statements resemble statements in computer programming languages, such as FORTRAN, PASCAL, and C. Variables in RTL statements correspond to wires and/or hardware registers, and operations in RTL statements correspond to the hardware logic. A “behavioral” RTL can be used to describe what a machine does (i.e., the functions it performs) without describing how the machine performs those functions, while a “structural” RTL can be used to describe a particular hardware implementation of a machine.
EDA tools typically allow circuit designers to specify circuit designs using HDLs. Such tools may, for example, accept an HDL specification of a circuit as an input and create, from the description, a hierarchical database representing the circuit design. The EDA tool may also display a graphical representation of the circuit design based on the HDL description. One example of such a tool for designing VLSI circuits is Virtuoso® Schematic Composer, available from Cadence Design Systems, Inc. of San Jose, Calif.
HDL circuit specifications may be used for testing circuits and circuit designs, as well as for fabricating the circuits themselves. For example, a software tool referred to as a “simulator” may simulate the operation of a circuit specified by an HDL circuit specification to verify that the circuit design is correct. Once verified using a simulator or other means, an HDL circuit model may be provided to a foundry to be used directly as manufacturing input for fabrication of the designed circuit.
The two most widely-used HDLs are Verilog and VHDL (Very High Speed Integrated Circuits (VHSIC) Hardware Description Language), both of which have been adopted as standards by the Institute of Electrical and Electronics Engineers (IEEE). VHDL became IEEE Standard 1076 in 1987 and Verilog became IEEE Standard 1364 in 1995. Another example of an HDL is Intel Hardware Description Language (iHDL), developed by Intel Corporation of Santa Clara, Calif.
Certain problems with conventional techniques for designing circuits using HDLs may be understood with reference to the three primary stages in the process of designing a computer processor. The first stage, as described above, is to write RTL statements describing the functions to be performed by the processor. The second stage is to design schematics of particular circuitry to perform the functions specified by the RTL statements written in the first stage. Schematics typically indicate electrical connectivity, field-effect transistor (FET) widths and lengths, and sometimes the wire widths of the circuit. Schematic design may be performed manually by human circuit designers or automatically by software. Although schematics may be generated more quickly when they are generated automatically, automatically-generated schematics tend to result in circuits that are less dense and slower than manually-generated schematics.
The third stage in microprocessor design is to draw “artwork,” which specifies the circuit in yet greater detail than schematics. In particular, circuit artwork typically indicates exact FET and wire positions, widths, and lengths, and, for wires, indicates which metal layer the wire should be fabricated on. Artwork, like schematics, may be generated either manually or automatically, with similar tradeoffs between design time and performance.
One problem with this multi-stage approach to processor design is that flaws or inefficiencies in the design may not become apparent until the second or third stage in the design process. If, for example, a flaw is identified during the third stage of the design process (artwork generation), it typically is necessary to: (1) return to the first stage and modify the RTL statements in an attempt to fix the identified flaw; (2) re-generate schematics and/or artwork based on the modified RTL statements; (3) re-analyze the schematics and/or artwork, and (4) repeat steps (1)-(3) as necessary until all identified design flaws have been eliminated or sufficiently mitigated. This iterative process can be tedious and time-consuming, particularly if the RTL statements, schematics, or artwork are generated manually.
One kind of design inefficiency that may be identified based on circuit schematics or artwork is an unacceptably long signal propagation delay in the circuit. Examples of software tools that performs timing analysis of circuits based on schematics are PathMill® and PathMill® Plus, available from Synopsys, Inc. of Mountain View, Calif.
It would be useful to identify the existence of an unacceptably long delay prior to the generation of schematics so that the RTL statements which describe the circuit may be modified in an attempt to reduce the delay to an acceptable level without the need to generate and analyze schematics. Some existing systems are capable of generating delay estimates based on RTL statements. An example of such a system is PrimeTime, available from Synopsys, Inc. of Mountain View, Calif. The delay estimates generated by such systems, however, are not accurate under all circumstances. As a result, such systems may fail to detect an unacceptably long delay at the RTL-generation stage of the design process, thereby requiring the generation and analysis of schematics, or even artwork, for accurate delay estimates to be made, with the attendant disadvantages described above.
What is needed, therefore, are improved techniques for performing timing estimation in circuits specified using hardware description languages.